The AI Accelerator Bottleneck Is Moving Downstream, Into Glass Cloth and 3D DRAM

Nittobo is tripling capacity at its Fukushima plant in Japan. The new supply will not reach the market until mid-2027, Tom's Hardware reported on 9 March. Prices for the material have risen between 20 and 30%, and lead times for downstream copper-clad laminates have stretched from a normal 8 to 10 weeks to beyond 20.

T-glass is a low-CTE glass cloth used in the organic core of IC substrates, the interconnect layer between a chip and its printed circuit board. It keeps large, high-heat chip packages dimensionally stable, which matters more as AI processors grow bigger and run hotter. E-glass, the cheaper alternative, is mainly used in lower-end chips like microcontrollers and older mobile processors. For massive 2.5D and 3D packaging, T-glass is the preferred option. That combination of properties and limited substitution turns a niche material into a supply chain chokepoint. The supply crunch is acute because of who is driving demand. Hyperscalers are ordering ever-larger chip packages that require more T-glass per unit.

According to Nvidia data cited by Tom's Hardware, interposer sizes have grown from 814mm² for the Hopper architecture to 1,700mm² for Blackwell, a 109% increase, with Rubin and Feynman scaling further. "With T-glass supply even more constrained now, suppliers are no longer providing lead times," Bill Ho, an analyst at Yuanta, told the publication.

Replacement is not straightforward. Bilal Hachemi, an analyst at Yole Group who tracks the IC substrate supply chain, said T-glass "has specific dielectric and CTE values that work better for the AI chips, especially for the organic core." He added that the substrate industry has historically run on thin margins, so even modest demand surges can trigger shortages.

Nittobo's response goes beyond Fukushima. It is doubling raw yarn capacity at its Taiwan plant and importing yarn back to Japan for cloth manufacturing, and it has struck a collaboration deal with Nanya Plastics to outsource some weaving. By 2027, roughly 20% of Nittobo's glass cloth is expected to be woven by Nanya, a competitor, which gives a sense of how tight the market is. Bank of America estimates Nittobo's electronic materials segment will nearly double sales from ¥40.9 billion ($266 million) in 2025 to ¥87.7 billion by March 2028, with operating margins approaching 48%.

Meanwhile, accelerator designers are attacking the memory wall from another direction. At Hot Chips 2026, d-Matrix presented Raptor, a 3D-DRAM accelerator for generative inference that stacks a TSMC N4 logic die on top of a 3D DRAM die using 36 um face-to-face stacking, according to ServeTheHome. The company sizes a 72-card scale-up rack to host a frontier model such as Kimi K3 at 1M context, with 32GB per card using 4-bit weights and an 8-bit KV cache.

The argument for vertical stacking is energy. On-die SRAM costs roughly 50 fJ, while 2.5D HBM4 systems run in the 2.5 to 5 pJ range when chip-level energy is included. Vertical 3D IO comes in at around 0.3 to 0.4 pJ, about 10 times lower than HBM, because it is a PHY-less millimeter-scale path rather than a centimeter-scale interposer route. d-Matrix cites a practical bandwidth ceiling around 20 TB/s for HBM4 packages.

Microsoft is taking a different route with Maia 200. The 3nm chip carries 140 billion transistors, 6 stacks of HBM3e, 7TB/second of HBM bandwidth, 10,000 TFLOPS of FP4 performance and a 750 Watt TDP, ServeTheHome reported from the same conference. It has no scale-out networking, only scale-up, with 128 racks and 6,000 chips in the demonstrated configuration.

Research efforts point further out. Stanford, Carnegie Mellon, Penn, MIT and SkyWater Technology built the first monolithic 3D chip in a U.S. foundry, with the prototype outperforming comparable 2D chips by roughly a factor of four, and simulations of taller designs showing up to twelve-fold improvement on AI workloads, according to Stanford Engineering.